DocumentCode
3549941
Title
An energy-efficient analog front-end circuit for a sub-1V digital hearing aid chip
Author
Kim, Sunyoung ; Lee, Jae-Youl ; Song, Seong-Jun ; Cho, Namjun ; Yoo, Hoi-Jun
Author_Institution
Dept. of Electr. Eng. & Comput. Sci.,, Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
fYear
2005
fDate
16-18 June 2005
Firstpage
176
Lastpage
179
Abstract
A low-power, energy-efficient analog front-end circuit is proposed and implemented for a digital hearing aid chip. It adopts the combined-gain-control (CGC) technique for an accurate preamplification and the adaptive-SNR (ASNR) technique for an improvement of dynamic range with low power consumption. The proposed analog front-end achieves 87-dB peak SNR and dissipates 60-μW from a single 0.9-V supply. The core area is 0.5-mm2 in a 0.25-μm standard CMOS technology.
Keywords
CMOS analogue integrated circuits; adaptive signal processing; analogue circuits; delta-sigma modulation; gain control; hearing aids; power consumption; 0.25 micron; 0.9 V; 60 muW; 87 dB; CMOS; accurate preamplification; adaptive SNR technique; analog front-end circuit; combined gain control technique; digital hearing aid chip; dynamic range improvement; Auditory system; Circuits; Energy efficiency; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN
4-900784-01-X
Type
conf
DOI
10.1109/VLSIC.2005.1469361
Filename
1469361
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