Title :
A 3.125-Gb/s sub-milliwatt CMOS signal detector circuit
Author :
Savoj, Jafar ; Roo, Pierte
Author_Institution :
Dept. of Data Commun., Marvell Semicond. Inc., Sunnyvale, CA, USA
Abstract :
This paper describes a 3.125-Gb/s signal detector circuit that activates a powered-down receiver on the arrival of incoming data. The signal detector operates at a clock speed lower than the incoming data rate to lower the power dissipation in stand-by mode. It uses a frequency-modulated clock generator, asynchronous to the data, alleviating the need for the recovered clock and allowing the receiver to remain in the low-power mode. The circuit is fabricated in a 0.15-μm CMOS technology over an area of 39 μm × 95 μm. The power dissipation is 700 μW.
Keywords :
CMOS integrated circuits; clocks; frequency modulation; signal detection; synchronisation; 0.15 micron; 2.5 Gbit/s; 3.125 Gbit/s; 39 micron; 700 muW; 95 micron; CMOS; circuit fabrication; clock recovery; frequency modulated clock generator; signal detector circuit; CMOS technology; Capacitors; Circuits; Clocks; Detectors; Diodes; Power dissipation; Sampling methods; Signal detection; Threshold voltage;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469366
