DocumentCode
3549964
Title
A six-port 57GB/s double-pumped nonblocking router core
Author
Vangal, Sriram ; Borkar, Nitin ; Alvandpour, Atila
Author_Institution
Microprocessor Technol. Labs, Intel Corp., Hillsboro, OR, USA
fYear
2005
fDate
16-18 June 2005
Firstpage
268
Lastpage
269
Abstract
A six-port four-lane 57GB/s router core features double-pumped crossbar channels and destination-aware channel drivers that dynamically configure based on the current flit destination. This enables 45% reduction in channel area, 23% overall chip area, and up to 3.8× reduction in peak channel power, depending on router traffic patterns. In a 150nm six-metal process, the 12.2mm2 core contains 1.9 million transistors and operates at 1GHz at 1.2 V.
Keywords
integrated circuit design; integrated circuit interconnections; multiport networks; network routing; 1 GHz; 1.2 V; 150 nm; 57 GBytes/s; crossbar channels; destination-aware channel drivers; double pumped nonblocking router core; router traffic patterns; CMOS technology; Frequency; Integrated circuit interconnections; LAN interconnection; Microprocessors; Paper technology; Pipelines; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN
4-900784-01-X
Type
conf
DOI
10.1109/VLSIC.2005.1469383
Filename
1469383
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