CONTEST: a concurrent test generator for sequential circuits

The application of a concurrent fault simulator to automatic test vector generation is described. As faults are simulated in the fault simulator, a cost function is simultaneously computed. A simple cost function is the distance (in terms of the number of gates and flip-flops) of a fault effect from a primary output. The input vector is then modified to reduce the cost function until a test is found. The authors present experimental results showing the effectiveness of this method in generating tests for combinational and sequential circuits. By defining suitable cost functions, they have been able to generate: (1) initialization sequences, (2) tests for a group of faults, and (3) a test for a given fault. Even asynchronous sequential circuits can be handled by this approach