1000 Bit bipolar shift register

The design of a bipolar shift register array using discretionary interconnection techniques is presented. The array which includes clock drivers and output buffer circuits interfaces directly with T²L and has a fanout drive capability of 10. It operates from D C. to 15 MHz at a power dissipation of only 4 mw per bit including all clock drivers. Eight separate registers and four separate clock frequencies are possible on a single array.