• DocumentCode
    3552885
  • Title

    The laminated overlay transistor, a status report

  • Author

    Amantea, R. ; Becke, H.W. ; White, J.P.

  • Volume
    14
  • fYear
    1968
  • fDate
    1968
  • Firstpage
    70
  • Lastpage
    72
  • Abstract
    Since the Laminated Overlay Transistor (LOT) was first reported at the IEDM in 1967 considerable advances have been made with regard to technology, device design, and performance of this "three-dimensional" transistor structure.
  • Keywords
    Breakdown voltage; Current measurement; Frequency; Gain measurement; Impurities; Laboratories; Predictive models; Semiconductor process modeling; Substrates; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1968 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1968.187998
  • Filename
    1475523
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3552885