The design of high-speed low-power digital circuits

Digital integrated circuits have been built which exhibit sub-nanosecond signal propagation delay times at 5 mW power dissipation, thus yielding a power-delay product figure of merit which is an order of magnitude lower than existing high-speed integrated circuits. Computer-aided device and circuit analysis (both D.C. and transient) was utilized to optimize the design of the circuits. The transistor equivalent-circuit models were tailored to the operating conditions of the digital circuits; however, within that operating range, all pertinent non-linearities in model parameters such as transistor base-spreading resistance and cut-off frequency, circuit resistor vahLes and signal swing were investigated, in order to gain insight into device and circuit operation.