A 150 NSEC access, 1024 word by 1 bit p-channel switched capacitor RAM

IGFET switched-capacitor memory cells form the heart of a fully decoded dynamic. 1024-word by 1-bit p-channel random access memory. With 10V drive circuitry, chip access time is measured to be 150 nsec and cycle time is 300 nsec. On-chip power dissipation at a 300 nsec cycle is 100 mW (100 mW per bit) and is correspondingly lower at lower speeds. Refresh power at 100°C is less than 1 µW/bit.