A high density overlapping gate charge coupled device array

In this talk a technique for constructing a high density overlapping gate charge coupled device array is described and experimental verification of the concept is presented. The technique involves forming an asymmetrical well within each gate region. A bit density advantage of nearly four to one compared with a standard poly-silicon overlapping gate structure is achieved; this comparison is based upon serpentine arrays using identical mask design rules in each case. A density greater than bits/inch²results using a minimum geometry length of five microns. The array structure will be described and array characteristics will be given and compared to standard overlapping gate arrays.