Amnesia in layered insulator FET memory devices

A retention time theory is developed for layered insulator FET (LIFET) memory devices in which the dominant cause of amnesia is attributed to tunnelling of charge back to the silicon. The theory incorporates the effect of surface states and the time dependence of the electric fields in the insulators. An equation for the threshold voltage correct to first order in the electric field is derived and solved exactly. To facilitate comparison with other theories, the solution is given in expressions valid over several decades of time. The solution predicts in agreement with experimental results that after a delay time which is exponentially dependent on the initial threshold voltage, the oxide thickness and the surface state density, the threshold voltage decays logarithmically eventually tailing off exponentially. In the logarithmic regime the decay rate varies as the inverse square of the oxide thickness, the square root of the trap depth and inversely as the rate at which the density of surface states increases. The calculated decay rate is found consistently to be lower for alumina devices than for nitride devices. The effect on the decay rate of trap depth, density of surface states, thickness of each of the two insulators, the dielectric constant of the thicker insulator and the initial threshold voltage are carefully examined and the results presented in the form of graphs and tables to provide guidance for memory product design.