CMOS optimization for radiation hardness

Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, we have undertaken a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits. The goals of our study are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Studying radiation effects in MOS devices increases our basic understanding of MOS device physics and the findings can lead to the improvement of conventional CMOS design as well as the achievement of radiation-hardened designs.