Operation and characterization of N-channel EPROM cells

This paper describes the operation and characterization of an N-channel, double-polysilicon gate MOS structure used in an electrically programmable read-only memory (EPROM). The tradeoffs for various structures with regard to writing ability, reading ability, fabrication complexity and ease of erasure are discussed. Measurements of the device are compared to the associated theory, and the sensitivity of the structure to various device parameters is described.