• DocumentCode
    3554164
  • Title

    Back-gate-input MOS - A new low-power logic concept

  • Author

    Asai, S. ; Masuhara, T. ; Nakamura, T.

  • Author_Institution
    Hitachi, Ltd., Kokubunji, Tokyo, Japan
  • fYear
    1976
  • fDate
    6-8 Dec. 1976
  • Firstpage
    185
  • Lastpage
    187
  • Keywords
    CMOS logic circuits; Delay effects; Insulation; Inverters; Logic circuits; Logic devices; Low voltage; MOSFET circuits; Power dissipation; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1976 International
  • Conference_Location
    Washigton, DC, USA
  • Type

    conf

  • DOI
    10.1109/IEDM.1976.189014
  • Filename
    1478726
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3554164