• DocumentCode
    3554265
  • Title

    Minimization of parasitic capacitances in VMOS transistors

  • Author

    Bhatti, I.S. ; Rodgers, T.J. ; Edwards, J.R.

  • Author_Institution
    American Microsystems, Inc., Santa Clara, Ca.
  • Volume
    22
  • fYear
    1976
  • fDate
    1976
  • Firstpage
    565
  • Lastpage
    568
  • Abstract
    Process techniques for the reduction of parasitic capacitances in VMOS transistors (1) have been developed. Significant reductions in gate to drain overlap capacitance and side wall component of the junction capacitance have been achieved for a high performance VMOS process.
  • Keywords
    Boron; Capacitance-voltage characteristics; Electrodes; Epitaxial layers; MOS devices; Parasitic capacitance; Protection; Silicon; Substrates; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1976 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1976.189107
  • Filename
    1478819
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3554265