MOSFETs with polysilicon gates self-aligned to the field isolation and to the source/drain regions

The fabrication procedure and device characteristics of MOSFETs having a unique gate electrode structure are described. The polysilicon gate electrode of the structure is self-aligned on its ends with respect to the conductive source and drain regions, and it is also self-aligned on its sides with respect to the nonconductive field oxide isolation regions. This double self-alignment feature results in a polysilicon gate electrode area that matches the channel region of the FET. Another novel feature of this device is a self-registering electtical connection between the gate and the metallic interconnection pattern. An oxidation barrier layer of silicon nitride is used to prevent oxidation over the gate. When the nitride layer is removed, the entire gate area is revealed for contacting by a metal line. This misregistration tolerant contacting technique and the doubly self-aligned gate electrode structure yield small FETs with increased packing density. The novel fabrication procedure can lead to the formation of nonplanar microstructural features which nevertheless can be controlled by proper choice of processing variables. The experimental electrical characteristics of the new FET structure are quite similar to those of larger area MOSFETs fabricated using more conventional methods.