DocumentCode
3554545
Title
Subnanosecond ED MOS IC using new technology
Author
Kobayashi, Y. ; Sakai, T. ; Arita, Y.
Author_Institution
Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan
Volume
23
fYear
1977
fDate
1977
Firstpage
597
Lastpage
597
Abstract
A new integrated MOS structure which is featured with high speed, low applied voltage, low power and high packing density has been developed using Elevated Electrode IC technology. The arsenic doped polysilicon with an overhanging edge is used as a part of gate electrode. In the metal evaporation process, the shadowed area under the edge separates the source, drain and gat electrodes without fine photolithography and etching processes.
Keywords
Delay effects; Electrodes; Etching; High speed integrated circuits; Lithography; Low voltage; Propagation delay; Ring oscillators; Telephony; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1977 International
Type
conf
DOI
10.1109/IEDM.1977.189329
Filename
1479409
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