An analysis of latch-up prevention in CMOS IC´s using an epitaxial-buried layer process

The use of a p⁺buried layer beneath the p-well in CMOS is evaluated for controlling latch-up (parasitic SCR action). It is shown that this structure typically reduces the parasitic npn transistor´s current gain by two orders of magnitude. The npn gain reduction is the principal mechanism for latch-up control. The npn has been studied using STRAP to numerically solve the transport equations. These simulations show the npn current gain to be primarily governed by the base-retarding field arising from the impurity gradient of the outdiffusing buried layer. A new wide-base lateral pnp model has been developed to accurately model the field enhancement of the parasitic lateral pnp´s current gain. Experimental confirmation of the lateral pnp model is given.