Electrically alterable hot-electron injection floating gate MOS memory cell with series enhancement

An electrically alterable, floating gate, non-volatile memory transistor has been developed, having a cell area of under 500µ², and using an advanced n-channel, polysilicon gate process. Cell programming occurs via hot-electron injection, exhibiting three distinct operating regimes. Erase, on the other hand is based on field emission from floating gate to control gate. The magnitude of electrical erase is determined by applied bias, device parameters and processing history, particularly the interlevel oxidation temperature. Analysis of experimental data shows that electrical erase does change programming characteristics significantly, and must be accounted for in circuit design. Memory retention, determined by thermal stress, is comparable to commercially available EPROMs. The memory cell exhibits better than 1000 cycle write/erase capability, with degradation in interlevel conduction being the principle factor limiting endurance. Read disturb is not a problem at 5V operation, but could become so at higher operating voltages.