Modelling inter-electrode capacitances in a MOS transistor

A technique to model interelectrode capacitances in a MOS transistor is described in this paper. The technique enables the derivation of the capacitances in a straightforward manner without having to make any arbitrary assumptions with respect to the fractional assignment of the distributed charge in the channel between the source and the drain. As an example of this technique, the interelectrode capacitances of an enhancement-mode MOS transistor operating in the linear region are determined. The technique can be extended to any multiterminal device.