STL Technology

The application of state-of-the-art bipolar I.C. device and process technologies to the fabrication of Schottky Transistor logic is discussed. The special requirements of a dual Schottky barrier-height metal system is reviewed and the performance and density of STL utilizing minimum features ranging from 5 µm to less than 1.5 µm is shown including minimum gate delays below .5 nsec and power-delay product below 50 femto-Joules. An example of an STL circuit implemented with an automatically routed gate array is shown.