• DocumentCode
    3554934
  • Title

    A high-performance MOS technology for 16K static RAM

  • Author

    Liu, S.S. ; Smith, R.J. ; Pashley, R.D. ; Shappir, J. ; Fu, C.H. ; Kokkonen, K.R.

  • Author_Institution
    Intel Corp., Santa Clara, Calif.
  • Volume
    25
  • fYear
    1979
  • fDate
    1979
  • Firstpage
    352
  • Lastpage
    354
  • Abstract
    A scaled double-poly MOS technology has been developed which features a static memory cell size of 1.5 mil2with 4µ design rules using conventional photolithographic techniques. The technology scales the gate oxide thickness to 400Å and poly-Si channel length to 2.1µ with arsenic source-drain and self-aligned poly-poly via contact. Four different types of transistors are implemented to enhance circuit design versatility. Hot electron failures and soft errors do not limit the applicability of the technology.
  • Keywords
    Circuit synthesis; Doping; Electrons; Graphics; Integrated circuit interconnections; MOS devices; Printers; Printing; Random access memory; Read-write memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1979 Internationa
  • Type

    conf

  • DOI
    10.1109/IEDM.1979.189623
  • Filename
    1480488
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3554934