DocumentCode
3555072
Title
LOGEX-an automatic logic extractor from transistor to gate level for CMOS technology
Author
Boehner, Michael
Author_Institution
Siemens AG, Munich, West Germany
fYear
1988
fDate
12-15 Jun 1988
Firstpage
517
Lastpage
522
Abstract
A program for automatic extraction of a gate-level description from a transistor-level description based on the layout of a CMOS VLSI circuit is presented. The extraction algorithm combines transistors to gates to arbitrary complexity without the help of any cell library. The resulting gate-level description provides the input for a digital logic simulator for further investigations
Keywords
CMOS integrated circuits; VLSI; circuit analysis computing; circuit layout CAD; integrated logic circuits; logic CAD; CMOS technology; LOGEX; VLSI circuit; automatic logic extractor; extraction algorithm; gate-level description; layout verification; program; transistor-level description; Automatic logic units; CMOS logic circuits; CMOS technology; Circuit simulation; Laboratories; Logic gates; Pins; Signal analysis; Switches; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
0-8186-0864-1
Type
conf
DOI
10.1109/DAC.1988.14809
Filename
14809
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