Capacitance measurement technique in high density MOS structures

A precise capacitance measurement technique is described. This technique is based on a principle of capacitively devided a.c. voltage measurement. In test devices, reference and test capacitors are connected in series, and intermidiate node signal is monitored by on chip linear sense amplifier. Utilizing the technique, various capacitances were measured, and quantitativery compared with a two dimensional numerical analysis. The results indicate that the technique is practical and accurate for evaluating capacitive elements in VLSI´s.