An EEPROM with PN junction in floating gate

An EEPROM with new structure for byte-erasing is presented. It consists of a floating gate with PN junction and two control gates, which are located above the P⁺and N regions in the floating gate, respectively. Writing is performed by an avalanche injection of electrons from the channel to the floating gate as done in the conventional n-ch FAMOS. Whereas the erasing is carried out by the avalanche injection of electrons from P⁺N junction in the floating gate to the control gate. The first insulating layer of this new device can be made of an SiO2film much thicker than that of EEPROM using tunnel injection, thus assuring excellent data retention and high manufacturing yields. This new device, in which one bit corresponds to a single transistor, can also store data at a high packing density.