Integrated high and low voltage CMOS technology

Novel, complementary high- and low-voltage MOS transistors are described. The high-voltage CMOS transistors were designed and fabricated using the same shallow well as that of low-voltage CMOS transistors, thus enabling integration of the devices without the use of dielectric isolation. The high voltage p-channel transistor is built inside of the n-type well and the p-type offset channel is used to separate the drain area from the gate, which has the same oxide thickness and threshold voltage as a low-voltage p-channel transistor. The high-voltage n-channel devices are built in the high resistivity p-type substrate, using an n-type offset channel to separate the N⁺-drain and the gate. The high- and low-voltage CMOS transistors were fabricated using 55-75 ohmcm, p-type substrate with a minimum channel length of 8 microns for the high-voltage and 2 microns for the low-voltage transistors. Drain to source breakdown voltages above 250V and above 25V have been demonstrated for the high-voltage and low-voltage transistors respectively.