Parasitic effect-free, high voltage MOS ICs with shielded source structure

A shielded source structure is proposed for complete elimination of both "parasitic bipolar effect" in high voltage NMOS transistors and "latch up effect" in low voltage CMOS logic circuits, that strictly limit the area of safety operation (ASO) and noise margin for high voltage MOS ICs. The proposed structure, characterized by a p⁺ground layer formed under an n⁺source layer, prevents forward-biasing of the source junction and, in consequence, parasitic bipolar transistor or SCR turn-on, even at the drain avalanche breakdown condition. To verify these advantages, a 4 bit, 80 µm long offset-gate high voltage NMOS transistor array and low voltage n-Well CMOS buffer circuits, both with shielded source structure, were experimentally fabricated on the same chip by the same process. Since high voltage NMOS transistors showed more than 600 V drain breakdown voltage with no secondary breakdown and CMOS logic part was confirmed to withstand "latch up", a truly parasitic effect-free, large noise immunity high voltage MOS IC was realized.