Resistor coupled Josephson logic full adder circuit

This paper reports the circuit design and experimental results of a one-bit full adder circuit constructed from a resistor coupled Josephson logic family. The full adder circuit uses dual rail logic with emphasis on high speed operation. EX-OR gates, composed of OR and AND gates with true and complementary inputs generate sum signals Sn and Sn. 2/3 MAJORITY gates with OR gates as isolation devices generate carry signals Cn and Cn. Computer simulations show a 55 ps add operation time with a 57 µW power dissipation per one-bit adder. The full adder circuit was fabricated using a Pb-alloy Josephson junction process with a 5 µm minimum feature size. The adder operates satisfactorily under all input conditions. This result demonstrates the RCJL potential for high speed binary operations.