DocumentCode
3556103
Title
Multi-level metallurgy for master image structured logic
Author
Geffken, Robert M.
Author_Institution
IBM General Technology Division, Essex Junction, VT
Volume
29
fYear
1983
fDate
1983
Firstpage
542
Lastpage
545
Abstract
A dense double-level metal interconnection process has been developed for application to master image structured logic products. The metal wiring pitches that are currently being produced, 5.0-µm metal 1 and 7.0-µm metal 2, are compatible with 2.0-µm lithography at other mask levels. These densities are achieved by use of a nitride-polyimide dual insulation scheme and second metal lift-off to achieve a unique overlapping via structure and elimination of metal borders. Details and rationale for the choice of the insulator/via etch scheme and second metal definition process are discussed. Finally, the influence of various topographical effects are also considered.
Keywords
Dry etching; Insulation; Integrated circuit interconnections; Logic circuits; Metal-insulator structures; Plasma applications; Sputter etching; Substrates; Wet etching; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1983 International
Type
conf
DOI
10.1109/IEDM.1983.190563
Filename
1483688
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