Title :
A new self-align technology for low noise GaAs MESFET´s - Sidewall-assisted pattern inversion technology
Author :
Hagio, M. ; Katsu, S. ; Takagi, H. ; Kazumura, M. ; Kano, G. ; Teramoto, I. ; Mizuno, Hidenori
Author_Institution :
Matsushita Electronics Corporation, Osaka, Japan
Abstract :
A new self-align technology suitable for GaAs low noise FET and MMIC fabrication is described. The process is essentially based upon the conventional sidewall technology and the pattern inversion technology so that the non-refractory metals can be used as the gate material. The experimental O.5µm gate FET fabricated using the new process exhibits such a high gm value as 220 mS/mm and a low NF value as 1.6 dB at 12 GHz.
Keywords :
Annealing; Dry etching; FETs; Fabrication; Gallium arsenide; Laboratories; MESFETs; MMICs; Resists; Semiconductor device noise;
Conference_Titel :
Electron Devices Meeting, 1984 International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1984.190677
