Latchup free CMOS using guarded Schottky barrier PMOS

A new CMOS technology for VLSI applications has been developed. The key feature of this technology is the realization of a self-aligned, diffused lateral guard-ring around PMOS PtSi Schottky barrier (SB) source and drain. The technology provides significant performance advantages over the previously reported SB PMOS. The presence of the diffused guard-ring allows full recovery of PMOS transconductance, while maintaining unconditionally latchup free CMOS operation. In addition, measurements on the guarded PMOS devices show stable threshold behavior, a reduction in junction current leakage as compared to the SB device, low source/drain resistance and superior short channel behavior due to the use of shallow junctions. The devices are named Trenched Schottky Barrier (TSB) PMOS because of the fabrication technique used. Two dimensional numerical simulations of the guarded TSB PMOS device and the parasitic bipolar transistors responsible for controlling latchup, behavior are in good agreement with experiment.