DocumentCode
3556366
Title
A P-type buried layer for protection against soft errors in high density CMOS static RAMs
Author
Momose, Hiroshi ; Wada, Tetsunori ; Kamohara, Itaru ; Isobe, Mitsuo ; Matsunaga, Junichi ; Nozawa, Hiroshi
Author_Institution
Toshiba Corporation, Kawasaki, Japan
Volume
30
fYear
1984
fDate
1984
Firstpage
706
Lastpage
709
Abstract
A shallow P-type buried layer has been applied to the poly Si load static memory cell in order to suppress α-particle induced soft errors. The effects of the P-type buried layer for suppression of carrier collection due to the funnelling field is verified by a transient 2-carrier 2-dimentional simulator. Various profiles for the buried layer have been tested for CMOS static RAM performances. By means of the optimized process, soft error rate is reduced by three orders of magnitude compared with that of the unprotected structure, and no performance degradation has been observed.
Keywords
Analytical models; Boron; Error analysis; Parasitic capacitance; Performance evaluation; Poisson equations; Protection; Random access memory; Read-write memory; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1984 International
Type
conf
DOI
10.1109/IEDM.1984.190821
Filename
1484592
Link To Document