Halo doping effects in submicron DI-LDD device design

The design of DI-LDD submicron channel devices is investigated, specifically focusing on the halo optimization for punchthrough and threshold falloff protection. Two dimensional numerical analysis is used to demonstrate the tradeoff between breakdown voltage and improved short channel threshold falloff as the halo concentration is increased. For a given halo doping level, there is a maximum permitted drain voltage for each channel length which is limited by avalanche breakdown, drain induced threshold lowering and punch-through. A window of useful halo doses is established from to about below which there is no significant improvement of the device and above which there is an unacceptable level of device degradation. A maximum Vdsversus channel length curve for the polysilicon gate DI-LDD MOSFET is obtained which implies that power supply voltage must be scaled by approximately the same factor as channel length for this type of device.