A direct SRAM soft-error cross-section simulation with two-dimensional transport calculations

An advance in the simulation methodology for memory circuit soft-error is accomplished by simultaneous calculation of transient charge transport and circuit response for the four cross-coupled CMOS transistors of a SRAM cell following a severe carrier density perturbation. By comparing the critical circuit voltage required for error immunity directly with the experiments, we circumvented limitations imposed by 2D approximation and uncovered upset mechanisms, which, if exploited, will lead to stabilization against upset. For voltages less than this critical value, we find spatial dependence for upset sensitivities, even within the same drain diffusions, from which the dependence of upset cross section on circuit supply voltage may be assessed.