• DocumentCode
    3556570
  • Title

    A highly latchup-immune 1 µm CMOS technology fabricated with 1 MeV ion implantation and self-aligned TiSi2

  • Author

    Lai, F.S. ; Wang, L.K. ; Taur, Y. ; Sun, Y.C. ; Petrillo, K.E. ; Chicotka, S.M. ; Petrillo, E.J. ; Polcari, M.R. ; Bucelot, T.J. ; Zicherman, D.S.

  • Author_Institution
    IBM General Products Division, San Jose, California
  • fYear
    1985
  • fDate
    1-4 Dec. 1985
  • Firstpage
    513
  • Lastpage
    516
  • Abstract
    A 1 µm n-well CMOS technology with high latchup immunity is designed, realized, and characterized. The main features of this technology are : 1 MeV ion-implanted retrograde n-well, buried contact, arsenic-phosphorous double diffused n+/n-junction, self-aligned TiSi2on gate and diffusions with nitride spacer, and thin p epi on p+substrate. This technology has been demonstrated via the successful fabrication of high-performance 64K CMOS SRAM chips. It is also observed that the silicide plays an important role in latchup prevention since it reduces the emitter efficiencies of parasitic bipolar devices.
  • Keywords
    CMOS technology; Electrical resistance measurement; Epitaxial layers; Etching; Implants; Ion implantation; MOS devices; Silicon; Substrates; Subthreshold current;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1985 International
  • Conference_Location
    Washington, DC, USA
  • Type

    conf

  • DOI
    10.1109/IEDM.1985.191016
  • Filename
    1485566
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3556570