VLSI Local interconnect level using titanium nitride

A local interconnect technology has been developed for VLSI CMOS applications using a titanium nitride layer. The technology has been realized by utilizing the titanium nitride layer that forms during the self-aligned titanium silicide process: which is used to simultanously reduce gate and junction sheet resistances to < 1 ohm/sq. Normally the TiN layer is discarded, but in this process the 0.1µm thick TiN layer is patterned and etched to provide local connections between gates and N+ and P+ junctions, with a sheet resistance of < 10 ohm/sq. This is accomplished without area consuming contacts or metal straps, and without any additional deposition steps, in addition to providing a VLSI version of the buried contact process, the technology results in self-aligned contacts and minimum geometry junctions, for reduced capacitance. The technology has been demonstrated by the fabrication of a CMOS VLSI memory with nearly half a million 1µm transistors.