Triple layered SOI dynamic memory

The vertically stacked layers of active devices are suitable for implementing various AI(Artificial Intelligence) systems. It is our novel proposal to utilize a number of recrystallized SOI (Silicon on Insulator) layers as dynamic memory planes adapted to the imager on-chip and it has been successfully realized as the linear cell memories with the triple layered CMOS structure. By introducing the interlayer routing and the interleaving control, the triple layered memory of a given chip size reveals its applicability to the image memory with a throughput two times higher and a storage capacity two times larger than those of the conventional one of the same size.