A versatile, high-performance, double-level-poly double-level-metal, 1.2-micron CMOS technology

Author

Parrillo, L.C. ; Cosentino, S.J. ; Mauntel, R.W. ; Bergami, B.A. ; Tobin, P.J. ; Baker, F.K. ; Poon, S. ; Yoshii, Y. ; Pintchovski, F. ; Sun, S.W. ; Liou, F.T. ; Alvis, J. ; Kearney, M. ; Swensor, M.

Author_Institution

Motorola, Inc., Austin, Texas

Volume

32

fYear

1986

fDate

1986

Firstpage

244

Lastpage

247

Abstract

We have developed an advanced CMOS technology for application in fast SRAMS, non-volatile memory, microprocessor and logic circuits. Features of the 1.2µm (gate and contact) double-level-poly, double-level-metal technology include a twin-well CMOS [1] structure in n- or p-type starting material, SILO isolation [2] for high packing density, 250 A thick gate oxide, 0.9µm-nominal-effective channel-length (Leff) NMOS devices with moderately lightly doped drains [3], optional LDD PMOS devices for high-voltage circuit applications, low-temperature-flow BPSG, a TiSi/TiN/Al contact and barrier metallurgy, and three-micron and four-micron first-and second-level-metal pitches respectively. Novel features of the technology include a single-mask dual-chanstop PMOS field-and-punch-through-implant scheme as well as disposable gate-sidewall spacers for LDD formation on CMOS devices. Reliability has been designed into the technology with emphasis on hot-carrier-protected transistors and metallization.

Keywords

CMOS logic circuits; CMOS memory circuits; CMOS technology; Isolation technology; Logic circuits; MOS devices; Microprocessors; Nonvolatile memory; Random access memory; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1986 International

Type

conf

DOI

10.1109/IEDM.1986.191160

Filename

1486418