DocumentCode
3557074
Title
An 0.8 µm CMOS technology for high performance logic applications
Author
Chapman, R.A. ; Haken, R.A. ; Bell, D.A. ; Wei, C.C. ; Havemann, R.H. ; Tang, T.E. ; Holloway, T.C. ; Gale, R.J.
Author_Institution
Texas Instruments Incorporated, Dallas, Texas
fYear
1987
fDate
6-9 Dec. 1987
Firstpage
362
Lastpage
365
Abstract
This paper reports on the process architecture and results of an 0.8µm 5V CMOS logic technology. The process, which is a factor of two faster than current 1.2µm CMOS technology, features seven optically patterned levels with 0.8µm geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels.
Keywords
Boron; CMOS logic circuits; CMOS technology; Implants; Leakage current; Logic circuits; MOS devices; Oxidation; Testing; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1987 International
Conference_Location
Washington, DC, USA
Type
conf
DOI
10.1109/IEDM.1987.191432
Filename
1487390
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