Experimental technology and characterization of self-aligned 0.1 µm-gate-length low-temperature operation NMOS devices

Results are presented from work aimed at demonstrating the feasibility of a Si FET technology in the 0.1µm gate length regime. Self-aligned, n-channel polysilicon gated MOSFETs were designed for optimum operation at cryogenic temperatures (77°K) with reduced power-supply levels. A variety of test chips were assembled and several wafers processed. Direct write electron-beam lithography was used to pattern all levels. The shortest devices fabricated had gate lengths of 70nm. Measured device characteristics yielded over 750mS/mm transconductance.