DocumentCode :
3557355
Title :
Refinemant verification of fair transition systems can contribute to PLTL model checking
Author :
Bellegarde, F. ; Chouali, S. ; Julliand, J.
Author_Institution :
Lab. d´´Informatique, Univ. de Franche-Comte, Besancon
fYear :
2005
fDate :
11-14 July 2005
Firstpage :
166
Lastpage :
175
Abstract :
We present a verification approach of dynamic properties under fairness assumptions by PLTL model checking over finite state reactive systems. The systems that we want to verify are specified through a top-down refinement process. They interact with an environment, which is described partly by fairness assumptions. We give a definition of the refinement under fairness assumptions and show how the verification of the refinement can be used as a preprocessor for the verification of the properties under fairness assumptions at the refined level. Indeed, the refinement verification distinguishes the fair executions. So, the verification of a PLTL property P can be model-checked only on the fair executions that are noticed during the refinement verification. We present how to adapt the standard PLTL model checking algorithm to the model which results from the refinement verification
Keywords :
finite state machines; formal specification; formal verification; refinement calculus; temporal logic; PLTL model checking; fair transition system; refinement verification; top-down refinement process;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Formal Methods and Models for Co-Design, 2005. MEMOCODE '05. Proceedings. Third ACM and IEEE International Conference on
Conference_Location :
Verona
Print_ISBN :
0-7803-9227-2
Type :
conf
DOI :
10.1109/MEMCOD.2005.1487911
Filename :
1487911
Link To Document :
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