Title :
Architecture optimization of an N-channel LDMOS device dedicated to RF-power application
Author :
Muller, D. ; Giry, A. ; Pache, D. ; Mourier, J. ; Szelag, B. ; Monroy, A.
Author_Institution :
STMicroelectronics, Cedex, France
Abstract :
The improvement of the dynamic performances of a RF LDMOS power amplifier (PA) is presented via the investigation of two device architectures differently optimized: LDMOSo1 and LDMOSo2. The diminution of the capacitance Cds was achieved on LDMOSo1. The reduction of key parameters such as the gate resistance Rg, and the capacitance Cgd was obtained on LDMOSo2. Both optimized architectures could be combined to gain on dynamic performances and complete the LDMOSFET optimization.
Keywords :
MOSFET; power MOSFET; power amplifiers; radiofrequency amplifiers; LDMOSFET optimization; LDMOSo1; LDMOSo2; N-channel LDMOS device; RF LDMOS power amplifier; RF power amplifier; architecture optimization; gate resistance; Electric variables; Electronic mail; Parasitic capacitance; Performance gain; Power amplifiers; Protection; Radio frequency; Radiofrequency amplifiers; Roentgenium; Transistors;
Conference_Titel :
Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD '05. The 17th International Symposium on
Print_ISBN :
0-7803-8890-9
DOI :
10.1109/ISPSD.2005.1487975
