Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application

This paper proposes a low-cost design-for-testability (DFT) structure for a classical charge-pump phase-locked loop (CP-PLL) circuit to allow simple digital testing. The proposed CP-PLL DFT structure uses the existing charge-pump circuit and voltage-controlled oscillator (VCO) as a stimulus generator and a measuring device, respectively. Thus, no extra test stimulus or measured instruments are required during testing. The primary advantage is that the analog blocks of the CP-PLL are unchanged and that the test output is purely digital, ensuring that the characteristics of CP-PLL are unaltered and that a suitable on-chip design can be developed using the proposed CP-PLL DFT structure. Fault simulation results indicate that the proposed CP-PLL DFT structure possesses high fault coverage (97.9%). In addition, the physical chip design is presented to show low area overhead (4.48%) and little degradation in performance.