Title :
Multisynchronous and Fully Asynchronous NoCs for GALS Architectures
Author :
Sheibanyrad, Abbas ; Greiner, Alain ; Miro-Panades, Ivan
Abstract :
Networks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs. NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area. This article describes two approaches to implementing a distributed NoC in a GALS environment.
Keywords :
asynchronous circuits; clocks; network-on-chip; GALS architecture; asynchronous NoC; multiprocessor SoC; multisynchronous NoC; network-on-chip; synchronous clock signal distribution; Access protocols; Bandwidth; Circuit topology; Clocks; Delay; Frequency synchronization; Integrated circuit interconnections; Laboratories; Metastasis; Network-on-a-chip;
Journal_Title :
Design Test of Computers, IEEE
DOI :
10.1109/MDT.2008.167
