Low-cost reconfigurable VLSI architecture for fast fourier transform

In this paper, a low-cost reconfigurable FFT processor employing novel dual-path pipelined shared memory architecture is presented. Based on this architecture, an elaborate memory configuration scheme is designed to make single-port SRAM available. Moreover, a mixed-radix butterfly unit is also designed, which makes the processor capable of multimode operation. Compared with previous ones, the proposed architecture can greatly reduce area. In addition, an optimized data scaling approach is proposed and the signal-to-quantization noise ratio (SQNR) of an 8K-point fixed-point FFT can achieve 52.7dB with the wordlength of 13bit. A test chip for DVB-T/H is implemented with the proposed architecture and fabricated in 0.18-mum single-poly six-metal CMOS process. The core area of this chip is 2.83mm² with the power dissipation of 25.8mW at 20MHz.