VLSI architecture for hierarchical 2D mesh representation for very low bit rate applications

Methods for object-based compression and composition of natural and synthetic video content are currently emerging in standards such as MPEG-4 and VRML. This paper shows VLSI architecture for generating Hierarchical 2D Mesh Representation for Very Low Bit Rate Application. The architecture uses a successive triangulation technique and produces the coding of the mesh nodes location as well as the associate motion vectors. The coding technique is based on the quadtree approach. The performance results show that the prototype can be used in the online application and the power consumption shows that it is good enough in the mobile application. Moreover, the number of bits used for the coding shows that the architecture is suitable for very low bit rate applications