A high-speed digital comb filter for ΣΔ analog-to-digital conversion

Author

Luh, Louis ; Choma, John, Jr. ; Draper, Jeffrey ; Chiueh, Herming

Author_Institution

Univ. of Southern California, Los Angeles, CA, USA

Volume

1

fYear

1999

fDate

1999

Firstpage

356

Abstract

A new approach for implementing a digital decimator for high-speed ΣΔ modulators is presented. With the use of carry-saved adders, this decimator is able to operate at high speeds while maintaining the same throughput. By using systematic modular design, this filter can be easily designed and implemented with any order and any length, which greatly reduces the time and effort for circuit design. A prototype of a fourth-order length-16 digital comb filter has been implemented with a 1.2 μm standard CMOS process. With a single 5 V power supply, this filter can operate at a frequency up to 115 MHz. The power consumption is about 35 mW and the active area is 1083×965 μm²

Keywords

adders; comb filters; digital filters; high-speed integrated circuits; sigma-delta modulation; 1.2 micron; 115 MHz; 35 mW; 5 V; active area; carry-saved adders; circuit design; digital decimator; high-speed digital comb filter; length; order; power consumption; sigma-delta analog-to-digital conversion; systematic modular design; Adders; CMOS process; Circuit synthesis; Digital filters; Digital modulation; Frequency; Power filters; Power supplies; Prototypes; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. 42nd Midwest Symposium on

Conference_Location

Las Cruces, NM

Print_ISBN

0-7803-5491-5

Type

conf

DOI

10.1109/MWSCAS.1999.867279

Filename

867279