• DocumentCode
    3560875
  • Title

    Complementary logic with 60 nm poly gate JFET for 0.5 V operation

  • Author

    Kapoor, A.K. ; Zhang, Wensheng ; Sonkusale, Sameer ; Liu, Yanbing ; Gregory, P. ; Sridharan, U.C. ; Stager, C. ; Eib, N. ; Xie, Zhong ; Vora, M. ; Prasad, Jagadish ; Thummalapally, D. ; CHOU, Remi

  • Author_Institution
    SuVolta, Inc., Los Gatos, CA, USA
  • Volume
    46
  • Issue
    11
  • fYear
    2010
  • Firstpage
    783
  • Lastpage
    784
  • Abstract
    Digital logic based on nanoscale complementary junction field effect transistors in silicon is reported in order to address scaling issues with CMOS. For the first time, complementary logic based on an enhancement mode JFET (cJFET), consisting of n- and p-channel JFET transistors built on bulk silicon and SOI with 60 nm gate length operating at 0.5 V has been demonstrated. Scalability of this technology has been confirmed by simulation of JFET devices with channel length equal to 16 nm.
  • Keywords
    CMOS digital integrated circuits; junction gate field effect transistors; logic circuits; silicon-on-insulator; CMOS; SOI; complementary logic; digital logic; nanoscale complementary junction field effect transistors; poly gate JFET; size 60 nm; voltage 0.5 V;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2010.0742
  • Filename
    5479717
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3560875