• DocumentCode
    3561208
  • Title

    Three-Dimensional Simulation of Charge-Trap Memory Programming—Part I: Average Behavior

  • Author

    Amoroso, Salvatore Maria ; Maconi, Alessandro ; Mauri, Aurelio ; Compagnoni, Christian Monzio ; Spinelli, Alessandro S. ; Lacaita, Andrea L.

  • Author_Institution
    Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
  • Volume
    58
  • Issue
    7
  • fYear
    2011
  • fDate
    7/1/2011 12:00:00 AM
  • Firstpage
    1864
  • Lastpage
    1871
  • Abstract
    This paper presents a detailed investigation of charge-trap memory programming by means of 3-D TCAD simulations accounting both for the discrete and localized nature of traps and for the statistical process ruling granular electron injection from the substrate into the storage layer. In addition, for a correct evaluation of the threshold-voltage dynamics, cell electrostatics and drain current are calculated in presence of atomistic doping, largely contributing to percolative substrate conduction. Results show that the low average programming efficiency commonly encountered in nanoscaled charge-trap memory devices mainly results from the low impact of locally stored electrons on cell threshold voltage in presence of fringing fields at the cell edges. Programming variability arising from the discreteness of charge and matter will be addressed in Part II of this paper.
  • Keywords
    Monte Carlo methods; circuit CAD; statistical analysis; storage management chips; technology CAD (electronics); 3D TCAD simulations; Monte Carlo simulations; atomistic doping; cell edges; cell electrostatics; cell threshold voltage; charge-trap memory programming; drain current; granular electron injection; nanoscaled charge-trap memory devices; percolative substrate conduction; statistical process ruling; three-dimensional simulation; threshold-voltage dynamics; Doping; Electron traps; Monte Carlo methods; Nanoscale devices; Programming; Substrates; Transient analysis; Atomistic doping; Monte Carlo simulations; charge-trap memory devices; semiconductor device modeling;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • Conference_Location
    5/12/2011 12:00:00 AM
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2011.2138708
  • Filename
    5766024