A 60-GHz CMOS Dual-Mode Power Amplifier With Efficiency Enhancement at Low Output Power

A 60-GHz dual-mode power amplifier (PA) with efficiency enhancement at low output power in 65-nm bulk CMOS is presented. The PA consists of two cascaded common-source driver stages and one transformer-based output stage. The dual-mode output stage is reconfigured into a stacked-transistor amplifier with a 2.5-V power supply in high-power (HP) mode for high-power-handling capability and a cascode amplifier with a 1.2-V power supply in low-power (LP) mode for efficiency enhancement at low output power. The measured results show that the presented PA achieves a small-signal gain of 23.5/21.3 dB, a saturated output power value of 17.6/11.4 dBm, a 1-dB output power value of 12.5/4.7 dBm, and a peak power-added-efficiency (PAE) value of 20.4%/13.3% in the HP/LP mode at 60 GHz, respectively. The PAE at 10-dBm output power is improved by 2.8x (10.6% versus 3.8%) by utilizing the LP mode compared with the HP-mode-only PA. The total chip area is 0.68 mm × 0.35 mm, including pads.