Title :
Analog circuit and device interaction in high-speed SerDes design in 16nm FinFET CMOS technology
Author :
Zhong, Freeman ; Sinha, Ashutosh
Author_Institution :
Avago Technol. Inc., San Jose, CA, USA
Abstract :
SerDes deals with data serialization, deserialization and channel equalization up to data rate of 28+Gb/s. Process technology and device characteristic greatly impacts architecture, circuit topology, and design merit of a SerDes. Several architecture choices, analog circuits, and techniques to mitigate undesired device characteristic in 16nm FinFET are discussed in this paper. With advanced CMOS technology and mitigation techniques, a prototype 28Gb/s SerDes was developed and demonstrated desired performance, power and die area.
Keywords :
CMOS integrated circuits; MOSFET; analogue circuits; FinFET CMOS technology; SerDes design; analog circuit; channel equalization; data serialization; deserialization; mitigation techniques; size 16 nm; Analog circuits; CMOS integrated circuits; CMOS technology; Decision feedback equalizers; FinFETs; Layout; Logic gates;
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
DOI :
10.1109/IEDM.2014.7046971
